CHIP DESIGN ACADEMY

Understand the complete journey from idea to silicon.

A rigorous learning system for digital, analog, physical-design, test, packaging and product engineers—with concepts, workflows, signoff checks, practical exercises and direct links to working tools.

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21

Deep modules

86

Engineering terms

6

Role-based paths

23

Hours of curriculum

THE LIFECYCLE AT A GLANCE

One connected engineering system

Every phase consumes controlled inputs, produces evidence and changes downstream risk. Study the handoffs—not isolated acronyms.

Requirements

Architecture

RTL

Verification

Synthesis & DFT

Floorplan

Place & Route

Signoff

Tapeout

Manufacturing

Post-silicon

CHOOSE YOUR ROLE

Learning paths with a professional outcome

21 modules

Complete Chip Designer

Students and engineers entering IC design

A guided journey from device physics and architecture through RTL, physical implementation, tapeout and silicon.

YOU WILL BE ABLE TO

Understand every major handoff and contribute effectively to a cross-functional chip program.

View path

7 modules

RTL & Verification Engineer

Digital front-end engineers

Master cycle-accurate design, interfaces, CDC, assertions, coverage, synthesis and timing-aware RTL.

YOU WILL BE ABLE TO

Deliver lint-clean, verifiable and implementation-aware RTL blocks.

View path

7 modules

Physical Design Engineer

Implementation and signoff engineers

Follow a netlist through constraints, floorplan, place-and-route, power integrity and physical verification.

YOU WILL BE ABLE TO

Diagnose and close timing, congestion, power and manufacturability tradeoffs.

View path

6 modules

Analog & Layout Engineer

Analog, custom and mixed-signal designers

Connect CMOS fundamentals, transistor sizing, robust simulation, matching layout, extraction and package effects.

YOU WILL BE ABLE TO

Build and verify a transistor-level block through post-layout analysis.

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5 modules

DFT & Product Engineer

Test, yield and product engineers

Connect scan and memory test to production screening, diagnosis, yield learning and silicon characterization.

YOU WILL BE ABLE TO

Design a test strategy that supports coverage, cost, quality and actionable diagnosis.

View path

10 modules

Chip Program Technical Lead

Architects, leads and engineering managers

Focus on requirements, cross-discipline handoffs, PPA evidence, risk, approvals and release governance.

YOU WILL BE ABLE TO

Lead a traceable chip program from requirements to validated silicon.

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COMPLETE CURRICULUM

Learn by lifecycle phase

Glossary Reference library

Lifecycle phase

21 curriculum modules

01 · Foundations

Foundation

Semiconductor and CMOS Fundamentals

Build the device-level intuition needed to reason about delay, power, noise margins, process variation and physical layout.

45 min

4 objectives

Study module

02 · Architecture

Foundation

Product Requirements and System Architecture

Translate a market problem into workloads, interfaces, PPA targets, safety requirements and an implementable chip architecture.

50 min

4 objectives

Study module

03 · Architecture

Intermediate

ISA, Microarchitecture and Datapath Design

Move from architectural behavior to pipelines, execution units, control, hazards, caches and measurable performance.

60 min

4 objectives

Study module

04 · Front End

Intermediate

RTL Design, Coding and Integration

Write synthesizable, portable and verifiable RTL with deliberate clock, reset, interface and parameterization choices.

60 min

4 objectives

Study module

05 · Front End

Intermediate

Functional Verification and Formal Methods

Plan, stimulate, observe and prove design behavior using simulation, coverage, assertions, formal analysis and disciplined closure.

70 min

4 objectives

Study module

06 · Front End

Advanced

Clock, Reset and CDC/RDC Design

Design reliable clock and reset domains, crossing protocols, synchronizers, constraints and structural verification.

55 min

4 objectives

Study module

07 · Implementation

Intermediate

Logic Synthesis and Design for Test

Map RTL into a technology library while preserving intent, meeting constraints and preparing controllable, observable silicon test structures.

65 min

4 objectives

Study module

08 · Signoff

Advanced

Constraints, Static Timing and MMMC Analysis

Model clocks, data paths, exceptions, variation and multiple operating scenarios to prove setup and hold timing.

75 min

4 objectives

Study module

09 · Physical Design

Intermediate

Floorplanning, IO and Power Intent

Turn the logical hierarchy into die/core geometry, macro placement, IO organization, voltage areas and a feasible power-delivery plan.

65 min

4 objectives

Study module

10 · Physical Design

Advanced

Placement, Clock-Tree Synthesis and Routing

Implement a legal, timed and routable physical design through placement, optimization, clock distribution and detailed interconnect.

80 min

4 objectives

Study module

11 · Signoff

Advanced

Power, IR Drop, EM, Thermal and Reliability

Analyze power consumption and ensure supply, interconnect, temperature and aging remain within lifetime limits.

75 min

4 objectives

Study module

12 · Signoff

Advanced

Physical Verification, Signoff and Tapeout

Prove geometric manufacturability, connectivity, timing, power integrity and release completeness before mask data handoff.

70 min

4 objectives

Study module

13 · Specialties

Advanced

Analog and Mixed-Signal IC Design

Design, simulate, lay out and verify transistor-level analog blocks and their interfaces with digital systems.

85 min

4 objectives

Study module

14 · Specialties

Intermediate

Memory Subsystems and IP Integration

Select, configure and integrate SRAM, caches, ROM, nonvolatile memory and third-party IP with correct interfaces, test and physical views.

60 min

4 objectives

Study module

15 · System Integration

Advanced

Packaging, Chiplets, SI/PI and Board Integration

Co-design die, package and board connectivity for power delivery, signal integrity, thermal performance, test and manufacturability.

75 min

4 objectives

Study module

16 · Manufacturing

Intermediate

Fabrication, Yield and Manufacturing Test

Understand wafer fabrication, process control, defect/yield economics, production test, characterization and quality feedback.

65 min

4 objectives

Study module

17 · Foundations

Intermediate

PDKs, Standard-Cell Libraries and Design Formats

Understand the process design kit and the logical, physical, timing, parasitic and mask-data views exchanged across the flow.

60 min

4 objectives

Study module

18 · Validation

Advanced

Post-Silicon Bring-up, Validation and Debug

Bring first silicon to life, characterize margins, diagnose failures and connect laboratory evidence back to design assumptions.

65 min

4 objectives

Study module

19 · Operations

Advanced

EDA Automation, AI and Engineering Governance

Build reproducible flows, use optimization and AI responsibly, track PPA regressions and retain evidence for human decisions.

60 min

4 objectives

Study module

20 · System Integration

Advanced

SoC Integration, Firmware and Emulation

Integrate processors, fabrics, peripherals, interrupts, address maps, boot firmware and hardware-assisted verification into a coherent SoC.

70 min

4 objectives

Study module

21 · Specialties

Advanced

Hardware Security, Safety and Assurance

Engineer trust boundaries, secure boot, key protection, fault response, side-channel resistance and safety evidence across the chip lifecycle.

75 min

4 objectives

Study module

FROM KNOWLEDGE TO EVIDENCE

Practice inside the same platform.

Each module links to calculators, analyzers, implementation flows and the governed workspace. Educational examples teach concepts; measured project artifacts support engineering decisions.

Open design workspace Explore RTL-to-GDSII flow