Physical Verification, Signoff and Tapeout
Prove geometric manufacturability, connectivity, timing, power integrity and release completeness before mask data handoff.
Overview
Physical verification checks that layout geometry follows foundry rules and matches intended connectivity. DRC, LVS, antenna, density, ERC and reliability checks complement timing, power and extraction signoff.
Tapeout is a controlled release, not a single clean report. It requires frozen versions, complete scenario coverage, reviewed waivers, reproducible artifacts, checksums, approvals and a handoff manifest.
Learning objectives
Distinguish DRC, LVS, ERC and antenna checks
Understand extraction and signoff inputs
Build a release checklist and waiver process
Preserve a reproducible tapeout evidence package
Core concepts
DRC
Geometry checks against process manufacturing rules.
LVS
Comparison of extracted layout connectivity and devices with the source netlist or schematic.
PEX
Extraction of parasitic resistance, capacitance and sometimes inductance from layout.
Antenna effect
Charge accumulation during fabrication that can damage thin gate oxide.
Density
Local layer coverage constrained for planarization and process uniformity.
Waiver
Reviewed acceptance of a specific finding with scope, evidence, owner and rationale.
Engineering workflow
Freeze inputs
Pin netlists, PDK, rule decks, libraries, constraints and tool versions.
• Release candidate
• Version manifest
Run physical checks
Execute DRC, LVS, ERC, antenna, density and extraction.
• GDS/OASIS
• Netlist
• Decks
• Verification reports
• Extracted views
Run signoff analyses
Close MMMC timing, power integrity, noise and reliability.
• Extracted design
• Signoff reports
Review and release
Resolve findings, control waivers, approve and checksum handoff.
• Evidence package
• Tapeout archive
• Release approval
Metrics and interpretation
DRC count
Violations grouped by rule and reviewed for uniqueness and severity.
LVS status
Net, device, parameter and connectivity equivalence result.
Antenna ratio
Process-specific conductor exposure relative to protected gate area.
Release completeness
Required artifacts and approvals present in the signed manifest.
Signoff checklist and pitfalls
Evidence checklist
- GDS/OASIS passes required foundry decks
- LVS is clean with approved black-box handling
- All signoff scenarios and extraction corners pass
- Waivers are specific, owned and approved
- Release archive is immutable, checksummed and reproducible
Common pitfalls
•
Calling a design clean from one DRC engine•
Using mismatched netlist and layout revisions•
Treating warnings as harmless without review•
Rebuilding artifacts after approval
Practice and platform tools
Construct a tapeout manifest listing source, netlist, GDS, constraints, PDK, libraries, reports, waivers, checksums, owners and approval gates.
References
OpenLane 2 reference manual
Efabless / OpenLaneFlow, step, configuration, design-state and signoff reference.
OpenROAD documentation
OpenROAD ProjectPrimary documentation for the open-source RTL-to-GDSII application and flow.
SKY130 open-source PDK
Google / SkyWater TechnologyProcess rules, device models, primitive cells and digital libraries for education and open flows.