Analog and Mixed-Signal IC Design
Design, simulate, lay out and verify transistor-level analog blocks and their interfaces with digital systems.
Overview
Analog design maps continuous-time specifications into device operating points, topology, biasing, compensation and noise performance. It relies on transistor models, corner analysis and layout-dependent effects.
Mixed-signal integration adds clocks, data converters, calibration, substrate coupling, supply noise and behavioral modeling. Matching, symmetry, shielding and guard structures are functional design elements—not cosmetic layout choices.
Learning objectives
Translate specifications into topology and device targets
Use gm/Id and small-signal reasoning
Plan matching-aware layout
Verify corners, Monte Carlo, stability and mixed-signal interfaces
Core concepts
gm/Id
Transconductance efficiency used to select inversion level and current density.
Loop stability
Closed-loop robustness evaluated with gain, phase margin and dynamics.
Matching
Relative accuracy of nominally identical devices, improved by geometry and layout techniques.
Common centroid
Interdigitated layout arrangement that cancels first-order gradients.
Monte Carlo
Statistical simulation of mismatch and process variation.
ENOB
Effective number of bits derived from converter signal-to-noise-and-distortion performance.
Engineering workflow
Allocate specifications
Translate system needs into block gain, noise, bandwidth, linearity and power.
• System model
• Block specs
Select topology and bias
Choose architecture and device operating regions.
• Specs
• PDK models
• Schematic
• Operating points
Simulate robustness
Run DC, AC, transient, noise, corners and Monte Carlo.
• Testbenches
• Performance distributions
Lay out and extract
Apply matching, shielding, guard rings and parasitic-aware verification.
• Schematic
• Rules
• Layout
• PEX simulation
• DRC/LVS
Metrics and interpretation
Gain-bandwidth
Amplifier gain and speed relationship under stated loading.
Phase margin
Distance from instability at unity loop gain.
Input-referred noise
Output noise translated to an equivalent input source.
Yield
Fraction of statistical samples meeting every required specification.
Signoff checklist and pitfalls
Evidence checklist
- All PVT and statistical requirements pass
- Bias and startup are verified
- Stability includes package/load extremes
- Layout matching and isolation intent is reviewed
- Post-layout extraction meets specifications
Common pitfalls
•
Optimizing typical schematic performance only•
Ignoring startup and power sequencing•
Using ideal sources and loads•
Treating post-layout simulation as a final formality