Chip Design Academy
Module 17
Foundations
Intermediate
60 minutes

PDKs, Standard-Cell Libraries and Design Formats

Understand the process design kit and the logical, physical, timing, parasitic and mask-data views exchanged across the flow.

WHY IT MATTERS

Overview

A process design kit is the controlled interface between a manufacturing process and design tools. It includes technology layers, device models, design rules, extraction decks, reliability limits and supported libraries.

Each design view answers a different question. RTL/netlist describe logic; Liberty describes timing/power; LEF/DEF describe abstract physical implementation; SPEF describes parasitics; SDC describes constraints; GDSII/OASIS describe final geometry. Version consistency is essential.

Learning objectives

Identify core PDK components

Match file formats to flow stages

Qualify standard-cell and macro releases

Prevent mixed-version collateral errors

TECHNICAL FOUNDATION

Core concepts

PDK

Foundry-qualified technology data, models, rules and decks consumed by design tools.

Liberty (.lib)

Cell function, timing arcs, constraints, power and operating-condition characterization.

LEF/DEF

Technology/cell abstracts and placed-routed design exchange formats.

GDSII/OASIS

Hierarchical polygon formats used for mask-data handoff and physical verification.

SPEF

Standard parasitic exchange format for extracted resistance and capacitance.

SDF

Standard delay format used for timing annotation into simulation.

INPUTS → DECISIONS → EVIDENCE

Engineering workflow

1
Select technology release

Choose process option, metal stack, voltage and supported flow.

INPUTS

Product needs

Foundry agreement

OUTPUTS

PDK baseline

2
Qualify libraries/IP

Check cells, corners, models, abstracts and provenance.

INPUTS

Library releases

OUTPUTS

Approved collateral

3
Map flow views

Define which version and format each tool consumes and produces.

INPUTS

Flow definition

OUTPUTS

View manifest

4
Control updates

Regression-test PDK/library changes and preserve release evidence.

INPUTS

New release

OUTPUTS

Compatibility report

Approval

MEASURE WHAT MATTERS

Metrics and interpretation

Corner coverage

Required process, voltage and temperature conditions with complete models.

View consistency

Logical, timing and physical views represent the same cell or macro release.

Deck version

Immutable identifier for DRC, LVS, extraction and reliability rule content.

REVIEW READINESS

Signoff checklist and pitfalls

Evidence checklist
  • PDK and libraries are approved for the target flow
  • All views have aligned version/checksum
  • Layer maps are correct across tools
  • Required corners and models are complete
  • Release notes and known limitations are reviewed
Common pitfalls
  • Mixing LEF and Liberty from different releases
  • Treating an open PDK as foundry support
  • Using typ-only characterization
  • Changing layer maps without full verification
LEARN BY DOING

Practice and platform tools

PRACTICAL EXERCISE
Create a view matrix for one standard-cell library and one SRAM macro showing every file, consumer, operating corner, version and checksum.
Library Explorer

Inspect standard-cell information.

Open tool
Liberty Parser

Explore timing and power models.

Open tool
GDS Remap

Review layer mapping.

Open tool
Cell Hierarchy

Inspect physical hierarchy.

Open tool
AUTHORITATIVE FOLLOW-UP

References


Continue learning
Foundations

Semiconductor and CMOS Fundamentals

Open module
Implementation

Logic Synthesis and Design for Test

Open module
Signoff

Physical Verification, Signoff and Tapeout

Open module