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Layout vs. Schematic
Clean demo
Broken demo
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Schematic (Verilog)
module top(a, b, sel, y); input a, b, sel; output y; wire t1, t2; AND g1 (.A(a), .B(sel), .Y(t1)); AND g2 (.A(b), .B(sel), .Y(t2)); OR g3 (.A(t1), .B(t2), .Y(y)); endmodule
Layout
3 cells · 6 wires · case=clean
Press
Run LVS
to compare the layout against the schematic. The broken-demo button intentionally drops a wire and adds an unconnected cell so the report has something to show.