Floorplanning, IO and Power Intent
Turn the logical hierarchy into die/core geometry, macro placement, IO organization, voltage areas and a feasible power-delivery plan.
Overview
Floorplanning determines die and core dimensions, utilization, aspect ratio, macro locations, placement blockages, routing channels and IO topology. These choices shape congestion, timing, power and routability.
Power intent defines voltage domains, isolation, retention, level shifting, power switches and legal power states. The physical power network must deliver current with acceptable voltage drop and electromigration margin.
Learning objectives
Estimate die/core area and utilization
Place macros using connectivity and channels
Plan IO, bumps and voltage domains
Create a PDN and early feasibility checks
Core concepts
Utilization
Placed standard-cell area divided by available placement area.
Aspect ratio
Core height-to-width relationship, affecting wirelength and routing distribution.
Halo/channel
Reserved space around or between macros for pins, buffers and routing.
Voltage area
Physical region implementing logic at a specific supply domain.
Power grid
Hierarchical rings, straps, rails and vias distributing supply and return current.
UPF
Power-intent description of domains, states, isolation, retention and supply relationships.
Engineering workflow
Estimate geometry
Reconcile cell, macro, IO, analog and margin area.
• Netlist
• Macros
• Package
• Die/core dimensions
Place macros and IO
Use connectivity, pin access, hierarchy and routing channels.
• Connectivity
• IO plan
• Macro floorplan
• Pin plan
Define power intent
Map power states and special cells to physical domains.
• Power architecture
• UPF
• Voltage areas
Build and analyze PDN
Size straps and vias using current estimates and early IR analysis.
• Activity
• Metal rules
• PDN
• IR/EM feasibility
Metrics and interpretation
Core utilization
Density target before detailed placement and routing effects.
Macro channel capacity
Available routing tracks relative to estimated demand.
Early IR drop
Estimated supply loss under representative current loading.
Pin accessibility
Ability of routing resources to reach macro and block terminals.
Signoff checklist and pitfalls
Evidence checklist
- Area reconciliation includes physical-only cells
- Macros have legal orientation, halos and channel capacity
- IO/package assignment is consistent
- Voltage areas and special cells match power intent
- PDN passes early IR/EM feasibility
Common pitfalls
•
Overaggressive utilization•
Macros placed by visual symmetry instead of connectivity•
Ignoring macro pin access•
Designing the package after die IO is frozen