Placement, Clock-Tree Synthesis and Routing
Implement a legal, timed and routable physical design through placement, optimization, clock distribution and detailed interconnect.
Overview
Placement assigns standard cells to legal sites while optimizing timing, wirelength, congestion, power and density. Clock-tree synthesis then constructs a controlled distribution network before signal routing finalizes geometry.
Global routing estimates paths and congestion; detailed routing assigns exact tracks, layers and vias under design rules. Each stage changes parasitics and timing, so optimization is iterative rather than a one-way sequence.
Learning objectives
Understand global and detailed placement
Balance skew, insertion delay and clock power
Interpret congestion and routing demand
Close timing and design rules iteratively
Core concepts
HPWL
Half-perimeter wirelength estimate from a net bounding box.
Legalization
Move cells to valid, non-overlapping sites while limiting displacement.
Skew
Difference in clock arrival time between sequential endpoints.
Useful skew
Intentional clock-arrival adjustment that improves timing while preserving correctness.
Global routing
Coarse allocation of nets to routing regions and layers.
Detailed routing
Exact track, wire and via assignment satisfying geometric rules.
Engineering workflow
Global placement
Optimize continuous or coarse cell locations for multiple objectives.
• Floorplan
• Netlist
• Constraints
• Placed density
• Early timing
Legalize and optimize
Snap cells to sites, size/buffer and repair congestion.
• Global placement
• Legal placement
Build clock network
Select topology, cells, routes and balancing targets.
• Clock sinks
• NDR rules
• Clock tree
• Skew report
Route and close
Perform global/detail routing, extraction and incremental repair.
• Placed design
• Clock tree
• Routed layout
• Parasitics
• DRC
Metrics and interpretation
Congestion overflow
Routing demand exceeding capacity in one or more regions.
Clock skew
Spread of clock arrival times for a defined sink group and scenario.
Insertion delay
Source-to-sink clock-network delay.
Via count
Layer transitions affecting resistance, yield, reliability and area.
Signoff checklist and pitfalls
Evidence checklist
- Placement is legal with acceptable density
- Congestion has no unmanageable hotspots
- Clock trees meet skew/latency and transition targets
- Routing is complete and antenna-aware
- Post-route timing and DRC converge together
Common pitfalls
•
Optimizing wirelength while creating timing hotspots•
Ignoring clock power•
Using broad placement blockages to hide congestion•
Timing closure based on pre-route parasitics