RTL & Verification Engineer
Digital front-end engineers
Master cycle-accurate design, interfaces, CDC, assertions, coverage, synthesis and timing-aware RTL.
Deliver lint-clean, verifiable and implementation-aware RTL blocks.
Your curriculum
Product Requirements and System Architecture
Translate a market problem into workloads, interfaces, PPA targets, safety requirements and an implementable chip architecture.
ISA, Microarchitecture and Datapath Design
Move from architectural behavior to pipelines, execution units, control, hazards, caches and measurable performance.
RTL Design, Coding and Integration
Write synthesizable, portable and verifiable RTL with deliberate clock, reset, interface and parameterization choices.
Functional Verification and Formal Methods
Plan, stimulate, observe and prove design behavior using simulation, coverage, assertions, formal analysis and disciplined closure.
Clock, Reset and CDC/RDC Design
Design reliable clock and reset domains, crossing protocols, synchronizers, constraints and structural verification.
Logic Synthesis and Design for Test
Map RTL into a technology library while preserving intent, meeting constraints and preparing controllable, observable silicon test structures.
Constraints, Static Timing and MMMC Analysis
Model clocks, data paths, exceptions, variation and multiple operating scenarios to prove setup and hold timing.
How to use this path
Complete each practical exercise, save evidence from the linked platform tools, and use every module’s checklist for a peer review before advancing.