Complete Chip Designer
Students and engineers entering IC design
A guided journey from device physics and architecture through RTL, physical implementation, tapeout and silicon.
Understand every major handoff and contribute effectively to a cross-functional chip program.
Your curriculum
Semiconductor and CMOS Fundamentals
Build the device-level intuition needed to reason about delay, power, noise margins, process variation and physical layout.
Product Requirements and System Architecture
Translate a market problem into workloads, interfaces, PPA targets, safety requirements and an implementable chip architecture.
ISA, Microarchitecture and Datapath Design
Move from architectural behavior to pipelines, execution units, control, hazards, caches and measurable performance.
RTL Design, Coding and Integration
Write synthesizable, portable and verifiable RTL with deliberate clock, reset, interface and parameterization choices.
Functional Verification and Formal Methods
Plan, stimulate, observe and prove design behavior using simulation, coverage, assertions, formal analysis and disciplined closure.
Clock, Reset and CDC/RDC Design
Design reliable clock and reset domains, crossing protocols, synchronizers, constraints and structural verification.
Logic Synthesis and Design for Test
Map RTL into a technology library while preserving intent, meeting constraints and preparing controllable, observable silicon test structures.
Constraints, Static Timing and MMMC Analysis
Model clocks, data paths, exceptions, variation and multiple operating scenarios to prove setup and hold timing.
Floorplanning, IO and Power Intent
Turn the logical hierarchy into die/core geometry, macro placement, IO organization, voltage areas and a feasible power-delivery plan.
Placement, Clock-Tree Synthesis and Routing
Implement a legal, timed and routable physical design through placement, optimization, clock distribution and detailed interconnect.
Power, IR Drop, EM, Thermal and Reliability
Analyze power consumption and ensure supply, interconnect, temperature and aging remain within lifetime limits.
Physical Verification, Signoff and Tapeout
Prove geometric manufacturability, connectivity, timing, power integrity and release completeness before mask data handoff.
Analog and Mixed-Signal IC Design
Design, simulate, lay out and verify transistor-level analog blocks and their interfaces with digital systems.
Memory Subsystems and IP Integration
Select, configure and integrate SRAM, caches, ROM, nonvolatile memory and third-party IP with correct interfaces, test and physical views.
Packaging, Chiplets, SI/PI and Board Integration
Co-design die, package and board connectivity for power delivery, signal integrity, thermal performance, test and manufacturability.
Fabrication, Yield and Manufacturing Test
Understand wafer fabrication, process control, defect/yield economics, production test, characterization and quality feedback.
PDKs, Standard-Cell Libraries and Design Formats
Understand the process design kit and the logical, physical, timing, parasitic and mask-data views exchanged across the flow.
Post-Silicon Bring-up, Validation and Debug
Bring first silicon to life, characterize margins, diagnose failures and connect laboratory evidence back to design assumptions.
EDA Automation, AI and Engineering Governance
Build reproducible flows, use optimization and AI responsibly, track PPA regressions and retain evidence for human decisions.
SoC Integration, Firmware and Emulation
Integrate processors, fabrics, peripherals, interrupts, address maps, boot firmware and hardware-assisted verification into a coherent SoC.
Hardware Security, Safety and Assurance
Engineer trust boundaries, secure boot, key protection, fault response, side-channel resistance and safety evidence across the chip lifecycle.
How to use this path
Complete each practical exercise, save evidence from the linked platform tools, and use every module’s checklist for a peer review before advancing.