Chip Design Glossary

Fabrication-time charge accumulation on interconnect that can damage a connected gate oxide.

AMBA Advanced Peripheral Bus, a low-complexity memory-mapped peripheral protocol.

Automatic test pattern generation for modeled structural faults.

AMBA Advanced eXtensible Interface for high-performance memory-mapped communication.

Back end of line: fabrication of contacts and metal interconnect above devices.

Built-in self-test logic that generates stimulus and checks responses on chip.

Bias temperature instability, an aging mechanism that shifts transistor parameters.

Clock-domain crossing between logic operating on different or asynchronous clocks.

A die intended as a component of a multi-die system-in-package.

Stopping clock transitions to inactive sequential logic to reduce dynamic power.

Difference in clock arrival time between sequential endpoints.

Chemical-mechanical planarization used to flatten wafer surfaces between process steps.

Cycles per instruction, a processor performance measure.

Clock-tree synthesis: construction and optimization of clock distribution.

Design Exchange Format describing placed and routed physical design data.

Design for test: structures and methods that improve manufacturing-test access.

Design rule checking of layout geometry against process constraints.

Dynamic random-access memory storing charge that requires periodic refresh.

Engineering change order: controlled modification after a design baseline.

Electromigration, current-driven atomic movement that limits interconnect lifetime.

Electrical rule checking for connectivity conditions such as floating nodes or invalid power connections.

Electrostatic discharge and the protection structures used to survive it.

Front end of line: formation of transistors and active devices.

Physical organization of die/core, macros, IO, domains and routing resources.

Mathematical proof or falsification of properties over a design state space.

Finite-state machine implementing state-dependent control behavior.

Hierarchical polygon layout format widely used for mask-data exchange.

Protected hardware relied on for foundational identity, measurement, key or verification functions.

A clock derived from a source clock with a defined waveform relationship.

Intentional margin protecting operation or quality against uncertainty.

Pre-designed physical block with fixed layout and characterized abstract views.

Minimum interval data must remain stable after the capturing clock edge.

Half-perimeter wirelength estimate from a net bounding box.

Supply voltage lost when current flows through PDN resistance.

Instruction-set architecture defining software-visible processor behavior.

IEEE-style test access architecture commonly used for boundary scan and debug.

Parasitic PNPN conduction that can create destructive supply current in CMOS.

Library Exchange Format for technology rules and abstract cell/macro physical views.

Standard cell timing, power and function characterization format, commonly .lib.

Transformation of RTL into an optimized technology-mapped gate netlist.

Layout-versus-schematic comparison of extracted and intended connectivity/devices.

Reserved placement space around a macro for routing and physical access.

Memory built-in self-test controller and algorithms.

Temporary unresolved state after a sequential element experiences a timing violation.

Multi-mode multi-corner analysis across functional modes and PVT/RC conditions.

Statistical simulation sampling process and mismatch variables.

Multi-project wafer run sharing mask and wafer cost among designs.

Mean time between failures, often used for synchronizer reliability.

Connectivity representation of instances, pins and nets.

Network-on-chip fabric providing routing, arbitration, ordering and quality of service between SoC agents.

Tolerance between valid logic levels and receiving thresholds.

On-chip variation modeling for delay differences across a die.

Compact hierarchical mask-layout exchange format.

Placement and routing of cells and interconnect.

Process design kit containing foundry technology models, rules and decks.

Power-delivery network of package, bumps, rings, straps, rails and vias.

Parasitic extraction from physical layout.

Loop-stability margin measured at unity gain.

Power, performance and area metrics used to compare implementations.

Specific process, voltage and temperature analysis condition.

Reset-domain crossing analysis for differing reset behavior.

Decoupled interface protocol where transfer occurs when ready and valid coincide.

Redistribution layer connecting die terminals to package-level geometry.

Register-transfer level description of cycle-based digital logic.

Switching Activity Interchange Format used for power estimation.

Shift-connected sequential elements used for manufacturing test.

Authenticated startup chain that executes only approved firmware and configuration.

Standard Delay Format used to annotate timing into simulation.

Synopsys Design Constraints format for clocks, IO delays and timing exceptions.

Minimum interval data must be stable before the capturing clock edge.

Pass/fail map across operating parameters such as voltage and frequency.

Information leakage through timing, power, electromagnetic or other physical behavior.

Preservation of waveform quality under loss, reflection, coupling and noise.

Difference between required and actual timing arrival; negative indicates a violation.

Standard Parasitic Exchange Format containing extracted R and C networks.

Static random-access memory implemented with bistable storage cells.

Static timing analysis of timing graph paths without input-vector simulation.

Pre-designed logic cell with aligned layout, timing and power views.

Controlled release of final mask-layout and signoff evidence to manufacturing.

Total negative slack summed across violating timing endpoints.

Unified Power Format describing power domains, states and special-cell intent.

Intentional clock-arrival differences used to improve path timing.

Value Change Dump simulation waveform format often used for activity.

Conductive connection between adjacent interconnect layers.

Worst negative slack across analyzed timing paths.

Fraction of manufactured units meeting defined acceptance criteria.