Physical Design Engineer
Implementation and signoff engineers
Follow a netlist through constraints, floorplan, place-and-route, power integrity and physical verification.
Diagnose and close timing, congestion, power and manufacturability tradeoffs.
Your curriculum
PDKs, Standard-Cell Libraries and Design Formats
Understand the process design kit and the logical, physical, timing, parasitic and mask-data views exchanged across the flow.
Logic Synthesis and Design for Test
Map RTL into a technology library while preserving intent, meeting constraints and preparing controllable, observable silicon test structures.
Constraints, Static Timing and MMMC Analysis
Model clocks, data paths, exceptions, variation and multiple operating scenarios to prove setup and hold timing.
Floorplanning, IO and Power Intent
Turn the logical hierarchy into die/core geometry, macro placement, IO organization, voltage areas and a feasible power-delivery plan.
Placement, Clock-Tree Synthesis and Routing
Implement a legal, timed and routable physical design through placement, optimization, clock distribution and detailed interconnect.
Power, IR Drop, EM, Thermal and Reliability
Analyze power consumption and ensure supply, interconnect, temperature and aging remain within lifetime limits.
Physical Verification, Signoff and Tapeout
Prove geometric manufacturability, connectivity, timing, power integrity and release completeness before mask data handoff.
How to use this path
Complete each practical exercise, save evidence from the linked platform tools, and use every module’s checklist for a peer review before advancing.