SDC Editor

clocks: 2
gen: 1
IO: 3
false: 1
MCP: 1
max/min: 1
Fmax: 100.0 MHz
Source
Clocks
NamePeriod (ns)Freq (MHz)Source
100.0clk
50.0clk_div

IO delays
KindClockDelay (ns)min/maxPorts
inputclk2.5max d_in
inputclk0.4 mind_in
outputclk1max q_out
Exceptions
TypeFromToDetail
false
reg_a/Qreg_b/D
MCP
a/CKb/D2 cyc
max
xy1.5 ns